Monothic Clock and Data Recovery Chip for 10gb/s Fiber Communications Systems

Clock recovery circuits which extract the clock signal from random NRZ data are very important to the multigigabit-per-second integrated receivers. Regarding the factors of flexibility and cost of implementation, phase-locked loops are standard approaches to CRCs. In a PLL, the phase detector is a key component which determines several significant properties of the PLL. The goal of this project is to compare the self-adjusting performance, noise performance, duty-cycle performance, and data-pattern dependence of several phase detectors, which are: Alexander PD [1], Hogge PD[2], and an improved Hogge PD designed in this project. The simulation tool is Matlab, which can verify the functionality of the circuit and provide a feasibility analysis within a reasonable time. We also compare the performance of the PLL with the PLL/DLL, which would enable jitter-free clock recovery.